Vendor Contributions in the Program

Wednesday

11:00 - 12:30 Session 8C

Chairs: Said Hamdioui (Delft University of Technology, NL), Giorgio Di Natale (LIRMM, F)

Improving Test Quality while Reducing DFT Costs Through a Hybrid ATPG + Logic BIST Solution
Martin Keim (Mentor Graphics, USA)

New Solutions for Reducing the Time, Effort and Cost of Quality SoC Testing
Rohit Kapur (Synopsys, USA)

ProChek: The Shortcut to Device and Process Qualification, Characterization, Comparison and Reliability Assessment
Hans Manhaeve (Ridgetop Europe nv, B)

Thursday

8:45 - 10:15 Session 10C

Chairs: Hans Kerkhoff (Twente University, NL), Xiaoqing Wen (Kyushu Institute of Technology, JP)

TSV BIST™: An Innovative Method for 2.5D / 3D IC Interconnection Integrity Monitoring
Hans Manhaeve (Ridgetop Europe nv, B)

Bit Error Rate Testing (BERT) using FPGA Assisted Test
Jan Heiber (GÖPEL electronic GmbH, D)

ELESIS towards Sophisticated Test Methods
Mohamed Azimane (NXP, NL)