ETS Workshops

The following three workshops will be co-located with ETS 2014 in Paderborn. All of them will take place in parallel from Thursday, May 29, 16:00, till Friday, May 30.

STEM Workshop: Statistical TEst Methods Workshop

General Chair: Manuel Barragan (TIMA, Grenoble, France)
Program Chair: Gildas Leger (Institute of Microelectronics of Seville, Seville, Spain)

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Brief description: Statistical test methods represent a promising step towards the reduction of the ever-increasing test costs for complex integrated systems. As opposed to traditional tests, based on extensive direct measurements, statistical test methods rely on building statistical models to infer the desired test information from simpler observables. Moreover, harvested statistical test data can be used to improve diagnosis and enable silicon-debug capabilities. The objective of this workshop is to provide an environment where researchers from academia and industry can discuss their latest findings, approaches, and ongoing work on all aspects of statistical test methods, from purely mathematical advancements to actual production test experiences.

RACING 2014: 1^st Workshop on Resource-Awareness and Adaptivity in Multi-Core Computing

General Chair: Jürgen Teich (University of Erlangen-Nuremberg, Germany)
Program Chair: Frank Hannig (University of Erlangen-Nuremberg, Germany)

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Brief description: The steady advances in semiconductor technology allow for increasingly complex SoCs, including multiple (heterogeneous) microprocessors, dedicated accelerators, large on-chip memories, sophisticated interconnection networks, and peripherals. However, design, verification, and test as well as parallel programming of such complex multi-core architectures are very challenging since they may have to deal with highly dynamic workloads in different application scenarios and environments. One recent research trend in multi-core computing is to design control loops across all platform layers – from application and run-time software down to the status of the underlying hardware. Concepts such as resource-aware programming and adaptive computing are promising candidates for optimizing multi-core systems at run-time with respect to several objectives (utilization, performance, temperature, energy, reliability, dependability, etc.) This workshop aims at bringing together researchers and experts from both academia and industry together to discuss and exchange research advances from different disciplines in design and test of multi-core architectures as well as programming and run-time management. A distinctive feature of the workshop is its cross section through the entire software/hardware stack, ranging from programming down to multi-core hardware.

TRUDEVICE Workshop on Test and Fault Tolerance for Secure Devices

General Co-chairs: Giorgio Di Natale (LIRMM, France) and Ilia Polian (University of Passau, Germany)
Program Chair: Marie-Lise Flottes (LIRMM, France)

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Brief description: Hardware security is becoming increasingly important for many embedded systems applications ranging from small RFID tag to satellites orbiting the earth. The vulnerability of hardware devices that implement cryptography functions has become the Achille’s heel in the last decade. This workshop will specifically target unique challenges of test and fault tolerance of secure devices and the non-trivial relationship between testability of a circuit and its protection against malicious attacks. The workshop will be co-located with a meeting within the framework of the COST Action IC1204 – TRUDEVICE (Trustworthy Manufacturing and Utilization of Secure Devices) and will facilitate the interaction between test and hardware security communities.

Important dates (for all three workshops):